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| 9-BIT HOLD REGISTER SY10E143 SY100E143 FEATURES s s s s s s 700MHz min. operating frequency Extended 100E VEE range of -4.2V to -5.5V 9 bits wide for byte-parity applications Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75k input pulldown resistors s Fully compatible with Motorola MC10E/100E143 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E143 are high-speed 9-bit hold registers designed for use in new, high-performance ECL systems. The E143 can hold current data or load new data. The nine inputs, D0-D8, accept parallel input data. The SEL (Select) control pin serves to determine the mode of operation; either HOLD or LOAD. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR. The E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation, and is also suitable for byte-wide parity. BLOCK DIAGRAM MUX D R Q0 PIN CONFIGURATION D0 D1 MUX R 25 24 23 22 21 20 19 D2 MUX D R Q2 MR CLK1 CLK2 VEE NC D0 D1 D8 D7 D6 D Q1 D5 VCCO Q8 SEL 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q7 Q6 VCC Q5 VCCO Q4 Q3 D D3 MUX R Q3 PLCC TOP VIEW J28-1 16 15 14 13 12 D D4 MUX R Q4 D D5 MUX R Q5 D D6 MUX R Q6 PIN NAMES Pin Function Parallel Data Inputs Mode Select Input Clock Inputs Master Reset Data Outputs No Connection VCC to Output D D7 MUX R Q7 D0-D8 SEL D8 SEL CLK1 CLK2 MR MUX D R Q8 CLK1, CLK2 MR Q0-Q8 NC VCCO D4 VCCO Q0 Q1 Q2 Rev.: D D2 D3 Amendment: /0 1 Issue Date: August, 1998 Micrel SY10E143 SY100E143 TRUTH TABLE SEL L H MODE LOAD HOLD DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 120 120 145 145 -- -- 120 120 145 145 -- -- 120 138 145 165 Min. Typ. Max. -- -- 150 TA = +25C Min. Typ. -- -- TA = +85C Typ. -- Max. 150 Unit A mA Condition -- -- Max. Min. 150 -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fMAX tPLH tPHL tS Parameter Max. Toggle Frequency Propagation Delay to Output CLK MR Set-up Time D SEL Hold Time D SEL Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25C Max. -- 1000 1000 -- -- -- -- -- -- -- 800 TA = +85C Min. Typ. 700 600 600 50 300 300 75 900 400 -- 300 900 800 800 -100 150 100 -150 700 -- 75 525 Max. -- 1000 1000 ps 50 300 300 75 900 400 -- 300 -100 150 100 -150 700 -- 75 525 -- -- -- -- -- -- -- 800 50 300 300 75 900 400 -- 300 -100 150 100 -150 700 -- 75 525 -- -- ps -- -- -- -- -- 800 ps ps ps ps -- -- 1 -- -- -- Unit MHz ps 600 600 800 800 1000 1000 600 600 800 800 Condition -- -- Min. Typ. Max. Min. Typ. 700 900 -- 700 900 tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E143JC SY10E143JCTR SY100E143JC SY100E143JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 2 Micrel SY10E143 SY100E143 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E143 SY100E143 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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